BT 900 Specifications download pdf (Page 22)

BT900-Sx Hardware Integration Guide

Intelligent BTv4.0 Dual Mode Module

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These signals operate according to normal industry convention. UART_RX, UART_TX, UART_CTS, and

UART_RTS are 3.3 V level logic (tracks VCC). For example, when RX and TX are idle they sit at 3.3 V.

Conversely for handshaking pins CTS, RTS at 0 V is treated as an assertion.

The module communicates with the customer application using the following signals:

 Port/TXD of the application sends data to the module’s UART_RX signal line

 Port/RXD of the application receives data from the module’s UART_TX signal line

Note

: The BT900 serial module output is at 3.3V CMOS logic levels (tracks VCC). Level conversion must be

added to interface with an RS-232 level compliant interface.

Some serial implementations link CTS and RTS to remove the need for handshaking. We do not recommend

linking CTS and RTS except for testing and prototyping. If these pins are linked and the host sends data when

the BT900 deasserts its RTS signal, there is significant risk that internal receive buffers will overflow, which

could lead to an internal processor crash. This drops the connection and may require a power cycle to reset the

module. We recommend that you adhere to the correct CTS/RTS handshaking protocol for proper operation.

Table 11: UART Interface

Signal Name

Pin No

I/O

Comments

SIO_1 / UART_TX 45 O SIO_1 (alternative function UART_TX) is an output, set high (in FW).

SIO_0 / UART_RX 44 I SIO_0 (alternative function UART_RX) is an input, set with internal

pull-up (in FW).

SIO_2 / UART_RTS 46 O SIO_2 (alternative function UART_RTS) is an output, set low (in FW).

SIO_3 / UART_CTS 1 I SIO_3 (alternative function UART_CTS) is an input, set with internal

pull-up (in FW).

The UART interface is also used to load customer developed

smart

BASIC application script.

UART has a deep buffer (UART_RX deep buffer) of 1024 bytes.

5.6 SPI Bus

The SPI interface is an alternate function on SIO pins, configurable by

smart

BASIC.

The module is a master device that uses terminals SPI_MOSI, SPI_MISO, and SPI_CLK. SPI_CSB is implemented

using any spare SIO digital output pins to allow for multi-dropping.

The SPI interface enables full duplex synchronous communication between devices. It supports a 3-wire

(SPI_MOSI, SPI_MISO, SPI_SCK,) bi-directional bus with fast data transfers to and from multiple slaves.

Individual chip select signals are necessary for each of the slave devices attached to a bus, but control of these

is left to the application through use of SIO signals. I/O data is double buffered.

The SPI peripheral supports SPI mode 0, 1, 2, and 3.

Table 12: Peripheral supports

Signal Name

Pin No

I/O

Comments

BT900

UART_TX

UART_RX

UART_CTS

UART_RTS

Application - Host

/RXD

/TXD

/RTS

/CTS

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 41 42

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